Semiconductor device

ABSTRACT

A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority fromprior Japanese Patent Application No. 2011-63875, filed on Mar. 23,2011, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device.

BACKGROUND

A DMOS transistor is known as one of power semiconductor devices.

The DMOS transistor comprises a drift region adjacent to a draindiffusion layer having a high impurity concentration. The drift regionhas the same conductivity type as that of the drain diffusion layer, andhas a lower impurity concentration than the drain diffusion layer. TheDMOS transistor is characterized in that its switching speed is fast ina relatively-low voltage region, and its conversion efficiency is high.The DMOS transistor may perform an operation with a high breakdownvoltage and a low ON resistance may be achieved at the same time.However, in such a DMOS transistor, an element termination region isformed at an end region of an element region where a DMOS transistoritself is formed. In some cases, an element termination region does nothave a predetermined breakdown voltage even when an element region hassuch a predetermined breakdown voltage.

In this case, the breakdown voltage of the whole element is determinedby the breakdown voltage of the element termination region. With theconventional DMOS transistor, concentration of an electric field occursin such an element termination region, and impact-ion due to this mayeasily be generated. As a result, a breakdown voltage of the wholesemiconductor device becomes lower. Therefore, a semiconductor devicehaving an element termination region with a high breakdown voltage isrequired. On the other hand, it is highly requested that a circuit areaof the whole semiconductor device is decreased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a structure of the semiconductor deviceaccording to the embodiment.

FIG. 2 is a plan view showing a structure of the semi conductor deviceaccording to the embodiment.

FIG. 3 is a plan view showing a structure of the semiconductor deviceaccording to the embodiment.

FIG. 4 is A-A′ B-B′ and C-C′ sectional views of FIG. 1-FIG. 3.

FIG. 5 is a plan view showing a structure of a comparative example.

DETAILED DESCRIPTION

A semiconductor device according to embodiments described hereinbelowincludes an element region formed on a semiconductor substrate andincluding an MOS transistor formed thereon, and an element terminationregion formed on the semiconductor substrate and formed at an end regionof the element region. A first semiconductor layer of a firstconductivity type is formed to extend in a first direction as itslengthwise direction from the element region to the element terminationregion. The first semiconductor layer has a first impurityconcentration, and functions as a drain region of the MOS transistor inthe element region. A second semiconductor layer of a first conductivitytype is formed to extend in a first direction as its lengthwisedirection from the element region to the element termination region. Thesecond semiconductor layer is formed in a layer below the firstsemiconductor layer, and has a second impurity concentration that issmaller than the first impurity concentration. A third semiconductorlayer of the first conductivity type is formed to extend in a firstdirection as its lengthwise direction from the element region to theelement termination region. The third semiconductor layer has a thirdimpurity concentration that is smaller than the second impurityconcentration. The third semiconductor layer is arranged in contact withthe second semiconductor layer and functions as a drift layer of the MOStransistor. A field oxide film is formed on a surface of the thirdsemiconductor layer and in contact with the first semicondutor layer. Afourth semiconductor layer of the second conductivity type is formed onthe semiconductor layer to extend in a first direction as its lengthwisedirection from the element region to the element termination region. Thefourth semiconductor layer functions as a channel region of the MOStransistor in the element region. A fifth semiconductor layer of thefirst conductivity type is formed on a surface of the fourthsemiconductor layer and functions as a source region of the MOStransistor. A gate electrode is formed on a surface of the semiconductorsubstrate between the third semiconductor layer and the fourthsemiconductor layer, via a gate insulating film. A distance between aboundary between the first semiconductor layer and the field oxide film,and the end portion of the third semiconductor layer on the side of thefifth semiconductor layer in the element region is smaller than adistance between a boundary between the first semiconductor layer andthe field oxide layer and an end portion of the third semiconductorlayer on the side of the fifth semiconductor layer in the elementtermination region.

The semiconductor device according to the embodiment is describedhereinbelow with reference to the drawings. Referring now to FIGS. 1-4,a laminated structure of the semiconductor device according to theembodiment is described. This semiconductor device relates to ap-channel type DMOS transistor.

It is possible that conductivity types of all of the semiconductorlayers in FIGS. 1-4 are reversed, thereby forming a an n-channel typeDMOS transistor formed on a P⁻ type substrate or p⁻ type semiconductorlayer.

FIG. 1 to FIG. 3 illustrate plan views of the semiconductor deviceaccording to the embodiment. FIG. 1 to FIG. 3 each illustrates some ofthe components in a selective manner to show positional relationshipamong overlapping components. Also, FIG. 4 shows A-A′, B-B′, and C-Csectional views of FIG. 1, FIG. 2, and FIG. 3. Note that in thefollowing discussion “p⁻ type” designates a semiconductor whose impurityconcentration is smaller than “P type”.

Also, “n⁻ type” designates a semiconductor whose impurity concentrationis smaller than “N type”.

As shown in FIG. 1, one semiconductor device of the present embodimentis formed, for example, on an N type semiconductor substrate 11. Thesemiconductor substrate 11 includes an element region R1 and an elementtermination region R2. The element region R1 is a region for forming a pchannel type DMOS transistor. The element termination region R2 isformed at the end region of the element region R1 in a first direction.Note that the semiconductor substrate 11 may be replaced by a p-typesubstrate.

As shown in FIG. 1, in the semiconductor device according to theembodiment, the element region R1 and element termination region R2 aredivided into a plurality of rectangular areas CP. The rectangular areasCP1, CP2, CP3 . . . are arranged to be aligned along the X-direction. Inaddition, each of the rectangular areas CP1, CP2, CP3 . . . has the samewidth Wcp in the X-direction.

The width of each of the rectangular areas CP in the element region R1and the width of each rectangular area CP in the element terminationregion R2 are both Wcp.

The semiconductor device of the present embodiment relates to animprovement in the shape of various components in such a rectangulararea CP. This improvement can supppress increase in circuit area. Also,a semiconductor device with a high breakdown voltage can be provided.

Also, as shown in FIG. 1, a gate electrode 18 is formed on thesemiconductor substrate 11 through a gate insulating film 18 a (notillustrated in FIG. 1). As an example, the gate electrode 18 is extendednot only in the element region R1 but also up to the element terminationregion R2. The gate electrode 18 is connected to a contact CSg in thiselement termination region R2, and is supplied with a necessary voltage.The gate electrode has a gate electrode length Lg1 in the element regionR1, and has a gate electrode length Lg2 (≠Lg1) in the elementtermination region R2. The gate electrode 18 is located such that it issandwiched by a P+ type drain region 12 functioning as a drain of thep-channel type DMOS transistor and a P+ type source region 15functioning as a source of the p-channel type DMOS transistor, along thegate length direction. There is formed a P type diffusion region 13 in alayer below the drain region 12.

Also, an N type diffusion region 16 is formed in a layer below thesource region 15 and a back gate diffusion region 19, as shown in FIG.3.

FIG. 4 shows A-A′, B-B′, and C-C′ sectional views of FIG. 1.

The A-A′ section is a section along the drain region 12 and the sourceregion 15 of the above-mentioned p channel type MOS transistor. The B-B′section is a section along the drain region 12 and the back gatediffusion region 19 of the p channel MOS transistor. The C-C′ section isa section of the element termination region R2 including the vicinity ofthe end portion of the drain region 12.

First, the structure of the p channel type MOS transistor along the A-A′section is described with reference to FIG. 4. As shown in the A-A′section of FIG. 4, the p channel type MOS transistor includes the P+type drain region 12. As shown in FIGS. 1-3, the P+ type drain region 12is formed to have a rectangular shape with the Y-direction (the firstdirection) as its lengthwise direction. The drain region 12 is arrangedin the vicinity of the center of the rectangular area CP along theX-direction. The drain region 12 extends from the element region R1 tothe element termination region R2. The P+ type drain region 12 isinjected with P type impurities such as boron (B), and has an impurityconcentration of 1e20 [cm⁻³], for example.

The P type diffusion region 13 is formed in a layer below the drainregion 12. The P type diffusion region 13 forms a a part of a drain ofthe p-channel type MOS transistor. The P-type diffusion region 13 isformed to extend from the element region R1 to the element terminationregion R2 in a Y-direction as its lengthwise direction.

The P type diffusion region 13 has an impurity concentration of about1e18 [cm⁻³] that is smaller than an impurity concentration of the drainregion 12. The P type diffusion region 13 has a width W1 in the elementregion R1 (see A-A′ sectional view of FIG. 4), whereas it has a width W2in an area in the vicinity of the end portion of the drain region 12 inthe element termination region R2 (see the C-C′ section of FIG. 4). Inaddition, a distance a1 from the end of the drain region 12 to the endof the P type diffusion region 13 in the A-A′ section is made smallerthan a distance a2 from the end of drain region 12 to the end of the Ptype diffusion region 13 in the C-C′ section. As an example, thedistance a1 is around 0.1 μm, and the distance a2 is around 0.3 μm.

The p-type drift region 14 is formed at a position beneath the gateelectrode 18 such that it contacts the P type diffusion region 13.

The p-type drift region 14 has an impurity concentration lower than animpurity concentration of the P type diffusion region 13, e.g., animpurity concentration of about 1e17 [cm⁻³]. The drift region 14 isformed to extend in the Y-direction as its lengthwise direction up tothe element termination region R2, like the drain region 12. However, awidth b1 of the drift region 14 from the junction of the P typediffusion region 13 in the A-A′ section is made smaller than a width b2thereof in the C-C′ section. In addition,

Also, a distance (a1+b1) from an end portion of the drift region 14 onthe source region 15 side to an end portion of the drain region 12 (aborder between the field oxide film 17 and the drain region 12) in theA-A′ section is smaller than a distance (a2+b2) from an end portion ofthe drift region 14 on the source region 15 side to an end portion ofthe drain region 12 (a border between the field oxide film 17 and thedrain region 12) in the C-C′ section. Accordingly, when a reverse biasis applied to the p channel MOS transistor, a depletion layer easilyspreads in the element termination region R2.

A field oxide film 17 composed of a silicon oxide film (e.g., SiO2 film)is formed on a surface of the P⁻ type drift region 14. The field oxidefilm 17 extends in the Y-direction as its lengthwise direction, and thewidth c1 thereof in the A-A′ section is made smaller than the width c2thereof in the C-C′ section. Note that the field oxide film 17 may beomitted, depending on a required breakdown voltage of the MOStransistor.

Also, an N type diffusion region 16 is formed at a position isolatedfrom the drift region 14 on the semiconductor substrate 11. The N typediffusion region 16 and the semiconductor substrate 11 between the Ntype diffusion region 16 and the drift region 14 function as a channelregion of this p channel type MOS transistor. The above-mentioned sourceregion 15 is formed on the surface of this N type diffusion region 16.The source region 15 is connected to a source electrode which is notillustrated through a contact plug CSs.

The N type diffusion region 16 is formed to extend in the Y-direction asits lengthwise direction, like the gate electrode 18 and the like (seeFIG. 3). The widths d1, d1′ of this N type diffusion region 16 in theelement region R1 are made smaller than the width d2, d2′ thereof in theelement termination region R2.

Like the gate electrode 18, the sourice region 15 is formed to extend inthe Y-direction as its lengthwise direction. The source region 15 islocated at the end portion in the X-direction of the rectangular areaCP. Note that the source region 15 is divided at certain positions inthe Y-direction, and the back gate diffusion region 19 is formed in thedivided position (B-B′ section), as shown in FIG. 2. The gate electrode18 is formed on the semiconductor substrate 11 through the gateinsulating film 18 a to extend over the drift region 14, the N typediffusion region 16, and the source region 15.

Sizes, impurity concentrations and the like of the drain region 12, theP type diffusion region 13, the drift region 14, and the source region15 may be set such that required characteristics such as an ONresistance, a breakdown voltage of the p channel MOS transistor in theelement region are satisfied.

The shape of the p channel type MOS transistor in the B-B′ section isapproximately similar to that in the A-A′ section. However, it isdifferent from that in the A-A′ section in that the source region 15does not exist in the B-B′ section, and, instead, the P+ type back gatediffusion region 19 is formed with a larger width.

As described above, the drain region 12, P type diffusion region 13, thedrift region 14 and the N type diffusion region 16 are formed to extendin the Y-direction from the element region R1 to the element terminationregion R2 (see the C-C′ section of FIG. 4). However, the width W2 of thep type diffusion region 13 along the C-C′ section is made larger thanthe width W1 thereof in the element region R1 including the A-A′section. Thus, as shown in a plan view of FIG. 1, the P type diffusionregion 13 has an expanded tip portion with a polygon shape, like amatchstick shape. Having such a shape, this embodiment may relaxconcentration of an electric field around the region R3 shown in FIG. 1,and suprres the generation of impact ions, thereby raising a breakdownvoltage of the MOS transistor. In addition, in the element terminationregion R2, the width b2 of the drift region 14 along the C-C′ section ismade larger than the width b1 thereof in the element region R1 includingthe A-A′ section. Due to this, in the element termination region R2, adepletion layer tends to spread more easily than in the element regionR1, thereby improving a breakdown voltage in the element terminationregion R2.

On the other hand, the width d2 of the N type diffusion region 16 alongthe C-C′ section is made smaller than the width d1 thereof in theelement region R1 including the A-A′ section. Decreasing the width ofthe N type diffusion region 16 in the element termination region R2 doesnot lower the breakdown voltage of the MOS transistor.

In this way, in the semiconductor device according to the presentembodiment, while the width W2 of the P type diffusion region 13 in theC-C′ section (in the element termination region R2) and the width b2 ofthe drift region 14 in the C-C′ section are made larger than those inthe element region R1. On the other hand, the width d2of the N typediffusion region 16 is made smaller. An element width in the elementtermination region R2 can be the same as that in the element region R1.Accordingly, various components can be acccomodated in the rectangularregion CP, as a whole.

The above-mentioned widths W2, b2, and d2 may be determinedirresppsctive of the widths W1, b1, d1 in the element region R1, andbased on a breakdown voltage required in the element termination region16. Even when the widths W2 and b2 are determined to have larger valuesthan those of the widths W1 and b1, respectively, the width d2 may bedetermined to be smaler than the width d1. Accordingly, the width of theelement termination region R2 along the X-direction need not be largerthan the width of the element region R1 along the X-direction.

In this way, according to the present embodiment, while the elementregion R1 may be designed to obtain a P channel MOS transistor thereinwith an optimized ON resistance or the like, the element terminationregion R2 may be designed to obtain a required breakdown voltage.

In above-mentioned embodiment, an example has been explained in whichthe width b2 is made larger than the width b1, and the width W2 is madelarger than the width W1. However, it is possible that only the width b2is made larger than the width b1, and the width W2 is made substantiallyequal to the width W1. This also allows the breakdown voltage of theelement termination region R2 to be raised.

However, enlarging the width W2 may contribute for preventing electricfield concentration in the end portion of the P type diffusion region13, thereby raising the breakdown voltage of the element. Accordingly,in addition to enlargement of the width b2, enlargement of the width W2may serve to raise the breakdown voltage of the element terminationregion even more.

FIG. 5 shows the planar shape of the element termination region in acomparative example of the present embodiment. In this comparativeexample, the width of the P type diffusion region 13 in the elementregion R1 is the same as that of the element termination region R2. Thisstructure cannnot prevent electric field concentration in the vicinityof the region R3 shown in FIG. 5. This causes the breakdown voltage inthe element termination region to lower, thereby lowering the breakdownvoltage of the semiconductor element as a whole. In this embodiment,because the width W2 of the P type diffusion region 13 in the elementtermination region R2 is expanded compared to the element region R1, thebreakdown voltage of the semiconductor device may be raised.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the inventions. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the inventions. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fail within the scope and spirit of the inventions.

1.-20. (canceled)
 21. A semiconductor device, comprising: asemiconductor substrate; a source layer formed on the semiconductorsubstrate; and a drain layer formed on the semiconductor substrate, thedrain layer being formed to face the source layer in a first directionwith a channel region and a drift layer therebetween, and the drainlayer being formed to extend in a second direction orthogonal to thefirst direction; wherein a distance along the first direction from thedrain layer to an edge of the drift layer on a side of the source layeris larger in an end portion of the drain layer than in a center of thedrain layer in the second direction.
 22. The semiconductor deviceaccording to claim 21, wherein the drift layer is formed to surround thedrain layer, and includes a first part in a vicinity of the center ofthe drain layer and a second part in a vicinity of the end portion ofthe drain layer.
 23. The semiconductor device according to claim 22,wherein the first part has a first width along the first direction, andthe the second part has a second width larger than the first width alongthe first direction.
 24. The semiconductor device according to claim 22,wherein the second part has a polygon shape.
 25. The semiconductordevice according to claim 22, wherein the first part is formed in anelement region including an MOS transistor formed thereon, and thesecond part is formed in an element termination region formed at an endregion of the element region.
 26. The semiconductor device according toclaim 22, further comprising a field oxide film formed on a surface ofthe drift layer.
 27. The semiconductor device according to claim 21,wherein the source layer, the drain layer and the drift layer have afirst conductivity type, and the impurity concentration of the driftlayer is lower than that of the drain layer.
 28. The semiconductordevice according to claim 21, further comprising a gate electrode formedon the channel region via an insulating film to surround the drainlayer, wherein a distance along the first direction from the drain layerto an edge of the gate electrode is larger in an end portion of thedrain layer than in a center of the drain layer in the second direction.29. A semiconductor device, comprising: a semiconductor substrate; asource layer formed on the semiconductor substrate; and a drain layerformed on the semiconductor substrate, the drain layer being formed toface the source layer in a first direction with a channel regiontherebetween, and the drain layer being formed to extend in a seconddirection orthogonal to the first direction; and a gate electrode formedon the channel region via an insulating film to surround the drainlayer, wherein a distance along the first direction from the drain layerto an edge of the gate electrode is larger in an end portion of thedrain layer than in a center of the drain layer in the second direction.30. The semiconductor device according to claim 29, wherein the gateelectrode is formed to surround the drain layer, and includes a firstpart in a vicinity of the center of the drain layer and a second part ina vicinity of the end portion of the drain layer.
 31. The semiconductordevice according to claim 30, wherein the first part has a first widthalong the first direction, and the the second part has a second widthlarger than the first width along the first direction.
 32. Asemiconductor device, comprising: a semiconductor substrate; a sourcelayer formed on the semiconductor substrate; and a drain layer formed onthe semiconductor substrate, the drain layer being formed to face thesource layer in a first direction with a channel region and a driftlayer therebetween, and the drain layer being formed to extend in asecond direction orthogonal to the first direction, wherein the driftlayer is formed to surround the drain layer, and includes a first partin the vicinity of the center of the drain layer and a second part inthe vicinity of the end portion of the drain layer, the second partbeing enlarged compared to the first part.
 33. The semiconductor deviceaccording to claim 32, wherein the first part has a first width alongthe first direction, and the the second part having a second widthlarger than the first width along the first direction.
 34. Thesemiconductor device according to claim 32, wherein the second part hasa polygon shape.
 35. The semiconductor device according to claim 32,wherein the first part is formed in an element region including an MOStransistor formed thereon, and the second part is formed in an elementtermination region formed at an end region of the element region. 36.The semiconductor device according to claim 32, further comprising afield oxide film formed on a surface of the drift layer.
 37. Thesemiconductor device according to claim 32, wherein the source layer,the drain layer and the drift layer have a first conductivity type, theimpurity concentration of the drift layer is lower than that of thedrain layer.
 38. The semiconductor device according to claim 32, furthercomprising a gate electrode formed on the channel region via aninsulating film to surround the drain layer, wherein the gate electrodeincludes a third part in the vicinity of the center of the drain layerand a fourth part in the vicinity of the end portion of the drain layer,an area surrounded by the fourth part is larger than that surrounded bythe third part.
 39. A semiconductor device, comprising: a semiconductorsubstrate; a source layer formed on the semiconductor substrate; and adrain layer formed on the semiconductor substrate, the drain layer beingformed to face the source layer in a first direction with a channelregion therebetween, and the drain layer being formed to extend in asecond direction orthogonal to the first direction; and a gate electrodeformed on the channel region via an insulating film to surround thedrain layer, wherein the gate electrode is formed to surround the drainlayer, and includes a first part in the vicinity of the center of thedrain layer and a second part in the vicinity of the end portion of thedrain layer, an area surrounded by the second part is larger than thatsurrounded by the first part.
 40. The semiconductor device according toclaim 39, wherein an area surrounded by the first part has a first widthalong the first direction, and an area surrounded by the second part hasa second width larger than the first width along the first direction.